Senior Logic Design Engineer

Job Summary

To support innovative technology development, the full-time Senior Logic Design Engineer will design and implement complex digital logic for FPGA and ASIC applications while collaborating with cross-functional teams in a remote environment.

Key responsibilities

• Design and implement complex, configurable, low-latency RTL modules using SystemVerilog
• Develop digital logic for high-performance FPGA and ASIC applications, including signal processing and real-time control
• Participate in the complete RTL development lifecycle, ensuring functional correctness and optimization of designs

Required qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical discipline
• 4+ years of professional experience in FPGA or ASIC digital logic design
• Strong practical experience in RTL development using SystemVerilog
• Solid understanding of digital logic design and RTL microarchitecture
• Experience with logic synthesis, static timing analysis (STA), and timing optimization