Senior Physical Design Engineer

Job Summary

Owning synthesis, timing convergence, and implementation readiness for key partitions across the AI accelerator roadmap, the full-time Senior Physical Design Engineer will be responsible for turning high-quality RTL into implementation-ready netlists while collaborating closely with RTL designers and backend implementation partners in a remote setting.

Key Responsibilities

• Manage synthesis for assigned partitions and subsystems, ensuring timely delivery of high-quality netlists
• Drive logical timing closure and optimize designs across frequency, area, power, and congestion
• Collaborate cross-functionally with architecture, RTL, verification, and physical design teams to resolve issues rapidly

Required Qualifications

• 8+ years of ASIC implementation experience with at least two successful tapeouts
• Strong proficiency in synthesis and flow development, particularly with Cadence Genus and/or Synopsys Design Compiler
• Proven experience in closing timing on complex, multi-million-gate designs
• Expertise in SDC constraints and advanced process nodes (7nm and below preferred)
• Strong Tcl and Python scripting skills for automation and flow development