Senior Physical Design Engineer

Job Summary

Owning synthesis, timing convergence, and implementation readiness for key partitions across the AI accelerator roadmap, the full-time Senior Physical Design Engineer will transform high-quality RTL into implementation-ready netlists and collaborate closely with RTL designers and backend implementation partners.

Key Responsibilities

• Own synthesis for assigned partitions, delivering clean, high-QoR netlists on schedule
• Drive logical timing closure for assigned partitions, optimizing across frequency, area, and power
• Collaborate with cross-functional teams to resolve issues rapidly and improve synthesis methodologies

Required Qualifications

• 8+ years of ASIC implementation experience, including at least two successful tapeouts
• Strong hands-on proficiency in synthesis and flow development using Cadence Genus or Synopsys Design Compiler
• Proven experience closing timing on complex, multi-million-gate designs
• Deep knowledge of SDC constraints and implementation-friendly coding practices
• Hands-on experience with advanced process nodes (7nm and below preferred)