Senior Physical Design Engineer

Job Summary

Owning synthesis, timing convergence, and implementation readiness for key partitions across the AI accelerator roadmap, the full-time Senior Physical Design Engineer will transform high-quality RTL into implementation-ready netlists while collaborating closely with RTL designers and backend partners.

Key Responsibilities

• Manage synthesis for assigned partitions, ensuring timely delivery of high-quality netlists
• Develop and maintain timing constraints, optimizing for frequency, area, power, and congestion
• Collaborate with cross-functional teams to address timing risks and enhance synthesis methodologies

Required Qualifications

• 8+ years of ASIC implementation experience with at least two successful tapeouts
• Proficiency in Cadence Genus and/or Synopsys Design Compiler
• Experience closing timing on complex, multi-million-gate designs
• Strong SDC expertise, including constraint development and MMMC environments
• Hands-on experience with advanced process nodes (7nm and below preferred)