Senior Staff ASIC Timing Engineer

Job Summary

Leading backend timing for photonics CMOS technologies, the full-time Senior Staff ASIC Timing Engineer will develop timing constraints, perform STA and timing closure, and sign off on tapeouts while collaborating with a team of engineers in a remote environment.

Key responsibilities

• Develop timing constraints and perform static timing analysis (STA) for photonics CMOS technologies
• Achieve timing closure and sign off on tapeouts, ensuring project deadlines are met
• Collaborate with architecture, RTL, and DFT groups to optimize power, performance, and area

Required qualifications

• Experience with Cadence or Synopsys tools for timing analysis
• Strong background in backend timing and physical design
• Proven track record of successful tapeout sign-offs
• Expertise in optimizing power, performance, and area in ASIC design
• Ability to document best practices for future projects