Senior Verification Engineer

Job Summary

To support advanced digital design projects, the contract Senior Verification Engineer will design and develop digital ASICs and FPGAs, implement verification methodologies, and collaborate with cross-functional teams in a fully remote capacity.

Key responsibilities:

• Own verification planning and execution for complex blocks and subsystems, ensuring test plans are completed through sign-off
• Develop verification environments, reference models, and coverage components while driving functional coverage closure
• Apply AI-assisted verification capabilities for stimulus generation and regression triage, mentoring junior engineers in verification methodology

Required qualifications:

• 7+ years of experience in ASIC design and implementation
• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical discipline
• Proficiency in HDL programming (VHDL, Verilog, and/or SystemVerilog)
• Experience with design verification and test bench development
• Familiarity with Linux development environments