SoC Design Verification Engineer

Job Summary

To support the complete verification of innovative System-on-Chip (SoC) designs, the full-time SoC Design Verification Engineer will develop verification plans, create testbenches, and ensure design quality and functional correctness in a remote work environment.

Key responsibilities

• Develop and execute verification plans for complex SoC digital designs
• Create and maintain UVM/SystemVerilog based testbenches and environments
• Perform functional coverage analysis and drive bug closure through regression runs

Required qualifications

• Bachelor's or Master's degree in Electrical, Electronics, or Computer Engineering (or related field)
• 5+ years of hands-on experience in ASIC/SoC design verification
• Strong proficiency in SystemVerilog, UVM, and simulation tools (e.g., Xcelium)
• Solid understanding of digital design fundamentals and RTL design
• Experience with scripting and programming languages (Python, Perl, TCL, C/C++)