Senior ASIC Floorplan Engineer

Job Summary

A company is looking for a Senior ASIC Floorplan Design Engineer.

Key Responsibilities

• Develop and optimize floorplans during early chip development in collaboration with various design teams
• Drive the area review process and identify improvement opportunities for area, interconnect, and floorplan
• Address timing and routing congestion issues by influencing design and physical implementation decisions

Required Qualifications

• Masters Degree in Electrical Engineering, Computer Science, or Computer Engineering or equivalent experience
• 6+ years of relevant work experience
• Deep hardware engineering background with a focus on VLSI and/or Computer Architecture
• Experience in Verilog, System Verilog or similar HVL
• Familiarity with CAD and physical design methodologies, including chip floorplan and timing closure